Conventionally, in semiconductor integrated circuit (IC) device production, a minimum required pattern of elements to be tested, referred to as the TEG (Test Element Group), is formed on a scribe area of the semiconductor wafer and then electrically probed to determine if the elements in the IC chips formed on the wafer are properly formed.
Since the TEG is made using the same process used to form the elements in the IC chips (to be separated by cutting in the scribe area), measurements of the electrical properties of the TEG are equivalent to measurements of the electrical properties of the elements in the IC chips. Thus, the properties of the IC chips can be accurately inferred by testing the TEG.
By placing the TEG in the wafer's scribe area, the number of IC chips which can be made from one semiconductor wafer is not reduced by the presence of the TEG.
FIG. 26 shows an example of a layout of IC chips to be formed on a silicon wafer 1. The wafer is divided in both the longitudinal and transverse directions by thin scribe areas (lines) 2, which are places where the wafer will be cut to separate the numerous individual long, thin IC chip areas 3 formed on the wafer. The chip areas 3 are grouped by 6 to form unit transfer patterns 4.
Many (in this case 36) unit transfer patterns 4 are formed on the wafer. The size of the transfer pattern 4 is approximately 17 mm (length).times.approximately 12 mm (width); (and the depth of an IC chip area is approximately 2 mm).
FIG. 27 shows a model of reticle (glass mask) forming a unit transfer pattern 4. A scribe area 2 is formed around each of the six IC chip areas 3. Each chip may contain ten or more to less than twenty pins for input terminals and 160 pins for output terminals (bond pad)). A TEG 5 is placed in area 2. The TEG 5 may be placed in the other scribe areas, as is partially shown in FIG. 27. In the FIG. 6 represents a block cell required to correctly transfer the reticle pattern.
The elements making up TEG 5 are indicated by the following abbreviations: LGN: Logic Gate N-ch Tr (n-channel transistor for logic gate); LGP: Logic Gate P-ch Tr (p-channel transistor for logic gate); VFN: Field N-ch Tr (field n-channel transistor); VFP: Field P-ch Tr (field p-channel transistor); RES: Resistor (resistor); CTS: Contact Chain (contact chain); LGC: Logic Gate Capacitor (capacitor for logic gate).
After completing the testing of TEG 5, which will be described later, IC chip 3 is separatedby cutting along the scribe lines 2 shown in FIG. 27. As shown in FIG. 28, both inner leads 8a and 8a' of a lead frame 8 formed on a polyimide film 7, are bonded to a bump electrode 15 (bump bond pad) using the TAB (Tape Automated Bonding) method. A package formed using this method is referred to as a TCP (Tape Carrier Package).
Three IC chips 3 on each side of the substrate 10 are bonded to connect them with matrix electrodes 11 and 12 of LCD 9 through the outer lead 8b as drivers for the 160.times.3 channel liquid crystal display (LCD) 9, which is shown in FIG. 29.
The IC chip 3 is sealed with a molded resin 13, such as an epoxy resin, and packaged (in FIG. 29, package 14 is shown). The IC chip 3 is bonded to the inner leads 8a and 8a' using the bump electrode 15. Both the inner lead 8a and the outer lead 8b provide output used for driving to LCD 9. Both the inner lead 8a' and the outer lead 8b' supply a specific input through a printed wiring substrate 16 (not shown in FIG. 29), which is connected to the outer lead 8b' to the IC chip 3.
FIG. 30 shows the pattern of the lead frame 8 using the above-mentioned TCP. The polyimide film 7 used as the carrier is cut by punching on the P-P' and Q-Q' lines. Both the inner lead 8a used for input and the inner lead 8a used for the output extend to the thin and long opening 7a. Their free terminals are bonded to the bump electrodes of IC chip 3.
In the following, the scribe area 2 shown in FIG. 27 and details concerning its surroundings are explained with reference to FIGS. 31 and 32.
As seen in FIG. 31, the scribe area 2 surrounds the IC chip area (active area) 3 where the input pad 17 and the output pad 18 are formed; a TEG 5 is placed on each of the scribe areas. The depth of the scribe area 2 is determined by the terminal of the protective film 25 (e.g., a silicon nitride film) of the IC chip.
After completing testing of the TEG, scribe area 2 is cut (diced) along A-A' and B-B' as the cutting ends with a blade whose width is either A-B or A'-B'. For example, diamond powder (approximately 5 .mu.m) may be impregnated in the outer circumference of a copper disk (approximately 35 .mu.m thick), then rotated at a high speed to saw the semiconductor wafer.
The TEG 5 consists of elements with various patterns. In FIG. 32, four types (VFP1, VFN1, LGP1, LGN1) are shown. MOS transistors that should be tested as elements are formed. In the figure, P represents a p-type diffusion area. N represents an n-type diffusion area. S represents the source electrode. D represents the drain electrode. G represents the gate electrode (The other elements are not described).
Each of the electrodes of the MOS transistor is introduced through wiring 20 to pads (terminal electrodes) 21, 22, 23, 24, . . . , on an insulating film 26. The probe needle is brought into contact with the pads, and the electrical properties of MOS transistors are measured by the probe test. The pads (21) and wiring 20 may be made of a metal (such as aluminum containing small amounts of additives; such as copper).
The inventors conducted investigations on TEG 5, and found that the following problems arose because the metal films of pads 21-24 . . . were cut along cutting positions A-A' or B-B' shown in the figure.
As seen in FIG. 33 (overviews of the required and major parts for the explanation are shown: from now on, the same), in the case in which scribing is done along A-A' and B-B' as the cutting ends, after completing the testing, to separate each of the IC chip 3 areas shown in FIG. 34, the pad 23 is continuously cut along its entire length along both A-A' and B-B', so a partial pad 23a remains in the end of the IC chip 3, and abatement of the pad metal (cutting burr) 23b are produced.
As the abatement 23b is produced based on the length of the pad 23, in the case in which the pad 23 is longer in the direction of cutting, the abatement 23b is long. Therefore, in the case of the above-mentioned pad 23, the abatement 23b must be long.
As seen in FIGS. 35-37, while abatement 23b is left, when the inner lead 8a of the lead frame is bonded through the bump electrode 15 to the output pad 18 (as in the case of input pad 17), which is formed on the insulating film 25 on the silicon substrate 27 of the IC chip 3 shown in FIG. 28, the above-mentioned long abatement 23b may come into contact with either inner leads 8a or 8a, resulting in an electrical short circuit either between the inner lead 8a and the semiconductor chip 3, or between both of the inner leads, resulting in the production of a defective IC chip 3.
A defect is likely to occur because, in the case of bonding using a TCP, the distance d between the lead 8a and the edge of the IC chip 3 (the distance d depends on the height of the bump electrode 15, and is usually 15-20 .mu.m, which is very short) is less than that for wiring bonding. Since the length (cutting depth) of the above-mentioned pad 23 along the cutting direction is 100 .mu.m, which is large, the abatement 23b produced by cutting is much longer than the above-mentioned distance d; this results the likelihood of short-circuiting.
In order to solve this problem, the above-mentioned production of the abatement may be prevented. A wide blade capable of covering and cutting the whole pad 23 can be used. However, in this case, the scribe area must be large enough for the wide blade, resulting in a decrease in the number of IC chips made from the semiconductor wafer.
Reducing the size of pad 23 such that it is smaller than the blade width, while maintaining the blade width, has been considered. However, there are limits to the reduction of the size of the pad 23 using the present technology. Therefore, the above-mentioned solution is not suitable.
The purposes of this invention are to provide a semiconductor wafer that does not give rise to faults, such as short-circuiting due to abatement, and that does not require any modification in the scribed width, blade width, or pad size when cutting conductive layers in a scribe area, such as the above-mentioned pads of the TEG, and to provide a semiconductor device made using the semiconductor wafer.